Asynchronous Self-checking Circuits

Asynchronous Self-Checking Circuits is a class of fault-tolerant digital circuits that autonomously detect logical errors during operation without relying on a global clock signal, distinguishing itself from synchronous counterparts by employing delay-insensitive or handshaking protocols to ensure correct operation under arbitrary timing variations while continuously verifying functional correctness through embedded redundancy and error-detection mechanisms.

11

Publications

376

Citations

36

Authors

19

Institutions

Publications per year

2017–2026

1

Authors

36

  1. SP
    S.J. Piestrak

    Wrocław University of Science and Technology, Poland

    2 publications · 50 citations

    2

    h-index

  2. MR
    Michel Raynal

    Institut de Recherche en Informatique et Systèmes Aléatoires, France

    1 publications · 17 citations

    1

    h-index

  3. AP
    A. Paschalis

    National and Kapodistrian University of Athens, Greece

    1 publications · 29 citations

    1

    h-index

  4. MS
    Milton Sawasaki

    IMEC, Belgium

    1 publications · 10 citations

    1

    h-index

  5. TH
    Thevenod

    1 publications · 12 citations

    1

    h-index

1–5 of 36

Venues

  1. Microprocessors and Microsystems

    MICPRO · 1 publications · 81 citations

    1

    h-index

  2. IEEE Design & Test of Computers

    1 publications · 20 citations

    1

    h-index

  3. IEEE Transactions on Electronic Computers

    1 publications · 10 citations

    1

    h-index

  4. Small

    1 publications · 61 citations

    1

    h-index

  5. IEEE Journal of Solid-State Circuits

    1 publications · 82 citations

    1

    h-index

1–5