Self-checking Logic

Self-Checking Logic is a digital circuit design methodology that belongs to the class of fault-detection techniques in digital systems, distinguished by its intrinsic ability to concurrently detect erroneous outputs through duplicated logic with mutual comparison, thereby ensuring correct functionality without external test equipment.

212

Publications

8.5K

Citations

307

Authors

137

Institutions

Publications per year

2017–2026

13

Authors

307

  1. CM
    Cecilia Metra

    University of Bologna, Italy

    17 publications · 456 citations

    13

    h-index

  2. MF
    M. Favalli

    University of Bologna, Italy

    11 publications · 301 citations

    11

    h-index

  3. BR
    B. Riccò

    University of Bologna, Italy

    10 publications · 247 citations

    10

    h-index

  4. MN
    M. Nicolaidis

    Techniques of Informatics and Microelectronics for Integrated Systems Architecture, France

    10 publications · 483 citations

    10

    h-index

  5. EM
    E.J. McCluskey

    Stanford University, United States

    9 publications · 361 citations

    9

    h-index

1–5 of 307

Venues

  1. IEEE Transactions on Computers

    49 publications · 2.6K citations

    27

    h-index

  2. 11

    h-index

  3. Journal of Electronic Testing

    JETTA · 5 publications · 267 citations

    6

    h-index

  4. IEEE Journal of Solid-State Circuits

    6 publications · 180 citations

    6

    h-index

  5. 5

    h-index

1–5