Self-checking Logic
Self-Checking Logic is a digital circuit design methodology that belongs to the class of fault-detection techniques in digital systems, distinguished by its intrinsic ability to concurrently detect erroneous outputs through duplicated logic with mutual comparison, thereby ensuring correct functionality without external test equipment.
212
Publications
8.5K
Citations
307
Authors
137
Institutions
Publications per year
2017–2026
13
Parents
212
Binary codes with specified minimum distance
M. Plotkin · IEEE Transactions on Information Theory · 1960 · 361 citations
Fault-tolerant computing: fundamental concepts
V.P. Nelson · Computer · 1990 · 360 citations
Design of dynamically checked computers.
William C. Carter, Peter R. Schneider · IFIP Congress · 1968 · 301 citations
1–5 of 212
307
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Techniques of Informatics and Microelectronics for Integrated Systems Architecture, France
10 publications · 483 citations
10
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9
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1–5 of 307
137
Techniques of Informatics and Microelectronics for Integrated Systems Architecture
Grenoble, France
17 h-index
38 publications
1.5K citations

University of Bologna
Bologna, Italy
13 h-index
51 publications
1.4K citations
Stanford University
Stanford, United States
12 h-index
20 publications
1.2K citations
University of Potsdam
Potsdam, Germany
10 h-index
26 publications
739 citations

Wrocław University of Science and Technology
Wroclaw, Poland
8 h-index
8 publications
135 citations
University of Rhode Island
Kingston, United States
8 h-index
12 publications
618 citations
Petersburg State Transport University
St Petersburg, Russia
7 h-index
10 publications
328 citations
Translational Innovation in Medicine and Complexity
Grenoble, France
7 h-index
10 publications
637 citations
1–8 of 137
49 publications · 2.6K citations
27
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11 publications · 658 citations
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JETTA · 5 publications · 267 citations
6
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6 publications · 180 citations
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5 publications · 334 citations
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