Delay-insensitive Circuits

Delay-Insensitive Circuits is a formal model of asynchronous digital circuits that belongs to the class of self-timed circuit designs and is distinguished by its independence from gate and wire delay parameters, ensuring correct operation regardless of propagation delays under all possible environmental and process variations.

225

Publications

10.6K

Citations

405

Authors

160

Institutions

Publications per year

2017–2026

9

Variants

Delay-insensitive Circuit

Authors

405

  1. MR
    Marc Renaudin

    Techniques of Informatics and Microelectronics for Integrated Systems Architecture, France

    11 publications · 576 citations

    11

    h-index

  2. SC
    Scott C. Smith

    University of Arkansas at Fayetteville, United States

    11 publications · 352 citations

    10

    h-index

  3. AJ
    Alain J. Martin

    California Institute of Technology, United States

    9 publications · 1.1K citations

    9

    h-index

  4. SM
    Steven M. Nowick

    Columbia University, United States

    7 publications · 173 citations

    7

    h-index

  5. RM
    Rajit Manohar

    Cornell University, United States

    7 publications · 94 citations

    7

    h-index

1–5 of 405

Venues

  1. IEEE Transactions on Computers

    10 publications · 684 citations

    10

    h-index

  2. 8

    h-index

  3. 7

    h-index

  4. IEEE Journal of Solid-State Circuits

    6 publications · 268 citations

    6

    h-index

  5. Electronics Letters

    5 publications · 114 citations

    5

    h-index

1–5