Delay-insensitive Circuits
Delay-Insensitive Circuits is a formal model of asynchronous digital circuits that belongs to the class of self-timed circuit designs and is distinguished by its independence from gate and wire delay parameters, ensuring correct operation regardless of propagation delays under all possible environmental and process variations.
225
Publications
10.6K
Citations
405
Authors
160
Institutions
Publications per year
2017–2026
9
Variants
Delay-insensitive Circuit
Parents
225
Asynchronous design methodologies: an overview
Scott Hauck · Proceedings of the IEEE · 1995 · 545 citations
Engineering, Computer Engineering, Electrical Engineering +12
Asynchronous Techniques for System-on-Chip Design
Alain J. Martin, M. Nystrom · Proceedings of the IEEE · 2006 · 305 citations
1–5 of 225
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Techniques of Informatics and Microelectronics for Integrated Systems Architecture, France
11 publications · 576 citations
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Techniques of Informatics and Microelectronics for Integrated Systems Architecture
Grenoble, France
11 h-index
35 publications
1.3K citations
Columbia University
New York, United States
11 h-index
25 publications
813 citations
California Institute of Technology
Pasadena, United States
9 h-index
19 publications
1.7K citations

University of Manchester
Manchester, United Kingdom
8 h-index
18 publications
715 citations
Missouri University of Science and Technology
Rolla, United States
8 h-index
19 publications
340 citations

Cornell University
Ithaca, United States
7 h-index
15 publications
311 citations

University of Arkansas at Fayetteville
Fayetteville, United States
7 h-index
29 publications
797 citations
Eindhoven University of Technology
Eindhoven, The Netherlands
7 h-index
7 publications
566 citations
1–8 of 160
10 publications · 684 citations
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8 publications · 712 citations
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7 publications · 154 citations
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6 publications · 268 citations
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5 publications · 114 citations
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