IEEE Transactions on Electron Devices · 1998 · 17 citations · 5 references
EngineeringElectrical EngineeringMaterials ScienceMicroelectronicsSemiconductor DevicesThin FilmsCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyIntegrated Circuit DesignSemiconductor Device MaterialsThin Film DiffusionThin-film TransistorsCmos Fabrication ProcessesDiffusion Layer GrowthGate Oxide Thickness EffectsSheet ResistanceSputteringSputtering EffectsSputtering TechniquesThermal Stability
A new cobalt (Co) salicide technology for sub-quarter micron CMOS transistors has been developed using high-temperature sputtering and in situ vacuum annealing. Sheet resistance of 11 /spl Omega///spl square/ for both gate electrode and diffusion layer was obtained with 5-nm-thick Co film. No line width dependence of sheet resistance was observed down to 0.15-/spl mu/m-wide gate electrode and 0.33-/spl mu/m-wide diffusion layer. The high temperature sputtering process led to the growth of epitaxial CoSi/sub 2/ layers with high thermal stability. By using this technology 0.15 /spl mu/m CMOS devices which have shallow junctions were successfully fabricated.
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Titanium disilicide self-aligned source/drain + gate technology
C. K. Lau, Y.C. See, D.B. Scott et al. · 1982 · 100 citations
A new salicide process (PASET) for sub-half micron CMOS
I. Sakai, H. Abiko, Hiroshi Kawaguchi et al. · 2003 · 28 citations