2002 · 63 citations · 18 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysReconfigurable ComputingBuilt-in Self-testConfigurable Logic BlocksDesign For TestabilityField-programmable Gate Array ArchitectureFpga ArchitectureProgrammable Logic DevicesField-programmable Gate Array TestabilityField-programmable Gate Arrays (Fpgas)Field-programmable Logic ArraysLogic BistProgrammable Logic ArrayProgrammable Logic DesignReconfigurable Logic BlocksSelf-test Architecture
We present an improved Built-In Self-Test (BIST) approach for the programmable logic blocks (PLBs) of a Field Programmable Gate Array (FPGA), which repeatedly reconfigures the FPGA as a group of C-testable iterative logic arrays. The new architecture is easily scalable with increasing size of FPGAs and ensures routability of the various configurations required to completely test the FPGA in three test sessions. In addition, the BIST approach addresses RAM mode testing as well as testing the adder/subtractor modes in FPGAs.
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Easily Testable Iterative Systems
Arthur Friedman · IEEE Transactions on Computers · 1973 · 253 citations
Testing for faults in combinational cellular logic arrays
William H. Kautz · 1967 · 175 citations