Field-programmable Gate Array Testability

Field-Programmable Gate Array Testability is a design-for-testability methodology that enables the systematic evaluation and enhancement of test access, fault detection, and diagnostic resolution specifically within reconfigurable digital circuits implemented on field-programmable gate arrays by integrating configurable test architectures and automated test pattern generation techniques tailored to their programmable interconnect and logic block structures.

144

Publications

4.4K

Citations

322

Authors

110

Institutions

Publications per year

2017–2026

10

Authors

322

  1. CE
    Charles E. Stroud

    University of Kentucky, United States

    16 publications · 704 citations

    15

    h-index

  2. MR
    M. Renovell

    Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, France

    17 publications · 658 citations

    13

    h-index

  3. FL
    Fabrizio Lombardi

    Northeastern University, United States

    14 publications · 476 citations

    12

    h-index

  4. YZ
    Y. Zorian

    Cirrus Logic (United States), United States

    12 publications · 567 citations

    11

    h-index

  5. JP
    J.M. Portal

    Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, France

    10 publications · 408 citations

    10

    h-index

1–5 of 322

Venues

  1. Journal of Electronic Testing

    JETTA · 5 publications · 111 citations

    5

    h-index

  2. IEEE Transactions on Nuclear Science

    4 publications · 79 citations

    4

    h-index

  3. IEEE Transactions on Computers

    3 publications · 59 citations

    3

    h-index

  4. 3

    h-index

  5. 3

    h-index

1–5