Pipelined Memory
Pipelined Memory is a memory modeling technique in computer architecture that belongs to the class of memory access optimization methods, specifically characterized by overlapping the stages of memory operations to improve throughput through concurrent processing of multiple memory requests.
113
Publications
3.8K
Citations
433
Authors
119
Institutions
Publications per year
2017–2026
8
Parents
113
19.7 A 16Gb ReRAM with 200MB/s write and 1GB/s read in 27nm technology
R. Fackenthal, Makoto Kitagawa, Wataru Otsuka et al. · 2014 · 213 citations
Engineering, Computer Engineering, Electrical Engineering +14
A single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP
B. Ackland, A. Anesko, D. Brinthaupt et al. · IEEE Journal of Solid-State Circuits · 2000 · 115 citations
1–5 of 113
433
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University of California, Santa Barbara, United States
3 publications · 107 citations
3
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3
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2
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1–5 of 433
119
University of Southern California
Los Angeles, United States
7 h-index
15 publications
596 citations
University of California San Diego
San Diego, United States
5 h-index
12 publications
570 citations
University of California, Irvine
Irvine, United States
4 h-index
11 publications
207 citations
Arizona State University
Tempe, United States
3 h-index
8 publications
117 citations
Intel (United States)
Santa Clara, United States
3 h-index
16 publications
1K citations
Stanford University
Stanford, United States
3 h-index
8 publications
158 citations
North Carolina State University
Raleigh, United States
3 h-index
4 publications
67 citations
Purdue University West Lafayette
West Lafayette, United States
3 h-index
7 publications
210 citations
1–8 of 119
15 publications · 562 citations
13
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4 publications · 129 citations
4
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3 publications · 91 citations
3
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TPDS · 3 publications · 134 citations
3
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2 publications · 61 citations
2
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1–5