Instruction-level Parallelism

Instruction-Level Parallelism is a form of parallel computing performance enhancement that belongs to the category of processor design techniques, specifically characterized by the execute-level overlap of multiple instructions within a single program stream through hardware or software mechanisms that identify and exploit independent operations.

1.6K

Publications

98.2K

Citations

3.2K

Authors

600

Institutions

Publications per year

2017–2026

Variants

Ilp

Parents

Computer Architecture

Children

Code MotionCommitControl Hazard MitigationData Hazard ResolutionDependence AnalysisExecution Latency HidingFunctional Unit SchedulingInstruction Fetch BandwidthInstruction Window ManagementIssue Width

Publications

1.6K

Validity of the single processor approach to achieving large scale computing capabilities

Gene M. Amdahl · 1967 · 4.2K citations

Engineering, Computer Engineering, Computer Science +17

MiBench: A free, commercially representative embedded benchmark suite

Matthew R. Guthaus, Jeffrey Ringenberg, Daniel Ernst et al. · 2001 · 3.1K citations

Engineering, Computer Engineering, Computer Science +17

MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems

1997 · 2.1K citations

Engineering, Computer Engineering, Computer Science +17

The Landscape of Parallel Computing Research: A View from Berkeley

Krste Asanović, Ras Bodik, Bryan Catanzaro et al. · 2006 · 2K citations

Engineering, Computer Science, High-performance Computing +17

MiBench: A free, commercially representative embedded benchmark suite

Matthew R. Guthaus, Jeffrey Ringenberg, Daniel Ernst et al. · 2005 · 1.6K citations

Engineering, Computer Engineering, Computer Science +17

1–5 of 1.6K

Authors

3.2K

GS
Gurindar S. Sohi
University of Wisconsin–Madison, United States
27 publications · 3.4K citations
24
h-index
SM
Scott Mahlke
University of Michigan, United States
31 publications · 1.7K citations
24
h-index
WH
Wen‐mei Hwu
University of Illinois Urbana-Champaign, United States
33 publications · 1.5K citations
24
h-index
MV
Mateo Valero
Universitat Politècnica de Catalunya, Spain
30 publications · 957 citations
20
h-index
YN
Yale N. Patt
The University of Texas at Austin, United States
21 publications · 2.2K citations
20
h-index

1–5 of 3.2K

Institutions

600

1–8 of 600

Venues

ACM SIGARCH Computer Architecture News
73 publications · 4.3K citations
36
h-index
IEEE Transactions on Computers
53 publications · 3.2K citations
30
h-index
IEEE Micro
34 publications · 3.2K citations
25
h-index
Computer
20 publications · 1.5K citations
20
h-index
ACM SIGPLAN Notices
30 publications · 2.3K citations
19
h-index

1–5