Issue Width
Issue Width is the maximum number of instructions that a processor can issue per clock cycle, distinguishing it from other microarchitectural metrics by quantifying the degree of parallel instruction initiation supported by the execution pipeline.
52
Publications
4.4K
Citations
99
Authors
37
Institutions
Publications per year
2017–2026
0
Variants
Instruction Issue Width
52
Complexity-effective superscalar processors
Subbarao Palacharla, Norman P. Jouppi, James E. Smith · 1997 · 839 citations
Multiple-banked register file architectures
José-Lorenzo Cruz, Antonio González, Mateo Valero et al. · 2000 · 423 citations · Full text
Lx: a technology platform for customizable VLIW embedded processing
Paolo Faraboschi, Gavin M. Brown, Joseph A. Fisher et al. · 2002 · 335 citations
1–5 of 52
99
7
h-index
5
h-index
5
h-index
4
h-index
3
h-index
1–5 of 99
37
Universitat Politècnica de Catalunya
Barcelona, Spain
7 h-index
16 publications
1.9K citations
University of Wisconsin–Madison
Madison, United States
5 h-index
11 publications
3.7K citations

Delft University of Technology
Delft, The Netherlands
4 h-index
8 publications
112 citations
The University of Texas at Austin
Austin, United States
4 h-index
8 publications
239 citations
Yale University
New Haven, United States
3 h-index
5 publications
128 citations
STMicroelectronics (United States)
Coppell, United States
3 h-index
3 publications
559 citations
Universidad de Zaragoza
Zaragoza, Spain
3 h-index
5 publications
171 citations
Hewlett-Packard (United States)
Palo Alto, United States
3 h-index
11 publications
1.9K citations
1–8 of 37
5 publications · 345 citations
5
h-index
Repository · 3 publications · 627 citations
3
h-index
3 publications · 143 citations
3
h-index
Conference · 1 publications · 11 citations
1
h-index
Conference · 1 publications · 16 citations
1
h-index
1–5