Concepedia

Functional Unit Scheduling

Functional Unit Scheduling is a processor-level control mechanism in superscalar architectures that determines the allocation and timing of instruction execution across multiple functional units by matching ready instructions with idle, compatible units to maximize instruction-level parallelism.

34

Publications

2.3K

Citations

103

Authors

39

Institutions

Publications per year

2017–2026

1

Parents

Publications

34

Force-directed scheduling for the behavioral synthesis of ASICs

Pierre Paulin, J.P. Knight · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1989 · 1.1K citations

, , +16

Global instruction scheduling for superscalar machines

David Bernstein, Michael Rodeh · 1991 · 183 citations · Full text

, , +16

An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors

Acosta, Kjelstrup, Torng · IEEE Transactions on Computers · 1986 · 101 citations

, , +15

Energy minimization with loop fusion and multi-functional-unit scheduling for multidimensional DSP

Meikang Qiu, Edwin H.‐M. Sha, Meilin Liu et al. · Journal of Parallel and Distributed Computing · 2007 · 91 citations

, , +16

Cyclone

Dan Ernst, Andrew J. Hamel, Todd Austin · 2003 · 78 citations

, , +17

1–5 of 34

Authors

103

  1. MH
    Mikko H. Lipasti

    University of Wisconsin–Madison, United States

    3 publications · 100 citations

    3

    h-index

  2. RA
    Robert A. Walker

    Montana State University, United States

    3 publications · 58 citations

    3

    h-index

  3. SR
    Samit Ray‐Chaudhuri

    Indian Institute of Technology Kanpur, India

    3 publications · 58 citations

    3

    h-index

  4. MR
    Michael Rodeh

    IBM Research - Haifa, Israel

    2 publications · 213 citations

    2

    h-index

  5. DB
    David Bernstein

    Princeton University, United States

    2 publications · 213 citations

    2

    h-index

1–5 of 103

Institutions

39

  1. University of Wisconsin–Madison

    Madison, United States

    4 h-index

    8 publications

    216 citations

  2. Rensselaer Polytechnic Institute

    Troy, United States

    3 h-index

    5 publications

    88 citations

  3. IBM Research - Haifa

    Haifa, Israel

    2 h-index

    4 publications

    426 citations

  4. Advanced Micro Devices (Canada)

    Markham, Canada

    2 h-index

    12 publications

    246 citations

  5. Carleton University

    Ottawa, Canada

    1 h-index

    1 publications

    1.1K citations

  6. Mercer University

    Macon, United States

    1 h-index

    1 publications

    65 citations

  7. Indian Institute of Science Bangalore

    Bengaluru, India

    1 h-index

    2 publications

    52 citations

  8. TU Wien

    Vienna, Austria

    1 h-index

    2 publications

    26 citations

1–8 of 39

Venues

  1. IEEE Transactions on Computers

    2 publications · 119 citations

    2

    h-index

  2. International Journal of Parallel Programming

    1 publications · 65 citations

    1

    h-index

  3. Journal of Marine Science and Engineering

    1 publications · 15 citations

    1

    h-index

  4. ACM Transactions on Embedded Computing Systems

    TECS · 1 publications · 11 citations

    1

    h-index

  5. 1

    h-index

1–5