Execution Latency Hiding is a method in computer architecture that belongs to the class of performance optimization techniques, specifically designed to overlap the execution of independent instructions to mitigate the impact of long-latency operations in out-of-order execution pipelines.
97
Publications
3.6K
Citations
298
Authors
106
Institutions
Publications per year
2017–2026
14
Publications
97
Performance of the CRAY T3E multiprocessor
E. Anderson, Jeff Brooks, C. M. Grassl et al. · 1997 · 135 citations
Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers
Seth H. Pugsley, Zeshan Chishti, Chris Wilkerson et al. · 2014 · 125 citations
1–5 of 97
Authors
298
- WH
6
h-index
- PRParthasarathy Ranganathan
Hewlett-Packard (United States), United States
4 publications · 80 citations
4
h-index
- SB
3
h-index
- JW
3
h-index
- PC
3
h-index
1–5 of 298
Institutions
106
University of Illinois Urbana-Champaign
Urbana, United States
10 h-index
27 publications
1.1K citations
University of Michigan
Ann Arbor, United States
5 h-index
15 publications
266 citations
Intel (United States)
Santa Clara, United States
5 h-index
13 publications
1K citations
University of Wisconsin–Madison
Madison, United States
4 h-index
10 publications
681 citations
University of California San Diego
San Diego, United States
4 h-index
10 publications
150 citations
University of Utah
Salt Lake City, United States
4 h-index
5 publications
461 citations
Uppsala University
Uppsala, Sweden
3 h-index
16 publications
348 citations
Tokyo Institute of Technology
Tokyo, Japan
3 h-index
10 publications
226 citations
1–8 of 106
Venues
- ACM SIGARCH Computer Architecture News
3 publications · 174 citations
3
h-index
- ACM Transactions on Computer Systems
TOCS · 3 publications · 63 citations
3
h-index
- IEEE Transactions on Computers
3 publications · 50 citations
3
h-index
- ACM SIGPLAN Notices
2 publications · 52 citations
2
h-index
- International Symposium on Microarchitecture
Conference · 2 publications · 59 citations
2
h-index
1–5