M. Jones

A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors

C.-H. Jan, S. Biswas, Markus J. Buehler et al. · 2008 · 45 citations

Engineering, Computer Engineering, Electrical Engineering +17

Random charge effects for PMOS NBTI in ultra-small gate area devices

M. Agostinelli, Sangwoo Pae, Wenxing Yang et al. · 2005 · 41 citations

Engineering, Computer Engineering, Electrical Engineering +17

The ideal SoC memory: 1T-SRAM/sup TM/

W.-B. Leung, Fu-Chieh Hsu, M. Jones · 2002 · 35 citations

Engineering, Computer Engineering, Electrical Engineering +16

Zero capacitor embedded memory technology for system on chip

S. Okhonin, P. Fazan, M. Jones · 2005 · 12 citations

Engineering, Computer Engineering, Electrical Engineering +10