Zero capacitor embedded memory technology for system on chip

Abstract

By harnessing the floating body (FB) effect of silicon on insulator devices, the authors introduced a true capacitor-less, single transistor DRAM - named Z-RAM <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">trade</sup> (zero capacitance DRAM) - which is capable of doubling memory density when compared to existing embedded DRAM technology (and achieving five times the density of current embedded SRAM), yet requires no exotic materials, no extra mask steps and no new physics. As no capacitor is required, the Z-RAM cell can readily be scaled as far as the transistor. The technology's bit-cell scalability was demonstrated at the 45nm node. It is easily envisaged that Z-RAM technology will scale well to at least the 22nm process node and ISi has already measured suitable characteristics in the FinFET transistors that may well be used at that time