2002 · 35 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesSystem-on-chip DesignEmbedded Memory BlocksIntegrated Circuit DesignInterconnect ArchitectureInterconnect DesignMemory DevicesEmbedded Memory IntegrationHigh-frequency OperationMemory Circuit DesignMetal Interconnect ScalingOn-chip Memory DesignProcess Technology SelectionStatic Random-access Memory DesignSystem-on-chip Architecture
The advances of process technology makes system-on-a-chip a reality and present major challenge to IC design. Integration of memory in SoC is further complicated by the incompatibility of memory process technology to the logic process. The simplicity of 1T-SRAM cell facilitates its easy porting to most processes. This helps alleviate the problem of process incompatibility. The simplicity of the cell structure also makes it extremely scalable and cost effective. The challenges of using this cell to satisfy the requirement of embedded SRAM are high-frequency operation, short latency, transparent refresh and soft-error rate. The use of multi-bank architecture and the leverage of multi-layer metal interconnect available in logic processes, allow these challenges to be met readily.