We report on scaled finFETs built with a novel routing scheme wherein devices are connected via buried power rails (BPRs) from both wafer sides, with tight variability and matching control. On the wafer’s frontside (FS), M1 lines (FSM1) are connected through V0 vias to M0A lines which are then linked to BPR lines by vias called VBPR while also contacting directly the device’s S/D-epi. As for gate wiring, to enable in this work its access from both wafer sides, gate is also connected to BPR via V0 landing on it and on a neighboring M0A line set only on field-oxide. A single-step metallization for M0A and VBPR is preceded by in situ preclean(s) optimized for improved BPR-VBPR contact interface and

${R}_{\text {ext}}$

, as confirmed electrically and by physical analysis. After FS processing, wafer flipping, bonding, and extreme thinning, highly scaled, ~323 nm deep nano-through-Si-vias (nTSVs) land on BPR, with tight overlay control and unchanged BPR resistance [26%–29% lower with improved tungsten (W)-fill], connecting them to the first backside (BS) metal level (BSM1). By moving the power delivery network to the BS (BSPDN), besides alleviating FS routing congestion, considerably smaller dynamic and static IR drop values are predicted from on- chip power heat maps generated for a low power 64-bit CPU at 2-nm design rules: 82% and 96% less worst-case values versus a reference configuration, respectively. P/NMOS show similar or even superior

${I}_{ \mathrm{\scriptscriptstyle ON}}$

–

${I}_{ \mathrm{\scriptscriptstyle OFF}}$

after BS processing and extra anneal(s) added for

${V}_{T}$

recovery, mobility and bias temperature instability (BTI) improvement—up to 8%/15% higher

${I}_{ \mathrm{\scriptscriptstyle ON}}$

linked to anneal selection.

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