Jim Tschanz - Concepedia

Concepedia

Author

Jim Tschanz

Intel (United States)

Also Known As

J. Tschanz, J.W. Tschanz, Jim Tschanz, Jim W. Tschanz

30

Publications

2.2K

Citations

17

H-Index

54

Concepts

All Affiliations

Intel (United States)Northwestern University

JT

About

Jim Tschanz is an author at Intel (United States) specializing in engineering, electrical engineering, and computer engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	17	21	2.2K
2	Computer Engineering	16	20	2.1K
3	Computer Science	4	4	152
4	Education	1	1	34
5	Social Sciences	1	1	37

Jim Tschanz

×

21

Publications

2.2K

Citations

17

H-Index

	Year	Citations
Parameter variations and impact on circuits and microarchitecture Shekhar Borkar, Tanay Karnik, S. Narendra, Hardware SecurityLow-power ElectronicsElectrical EngineeringPhysical Design (Electronics)Engineering	2003	1.4K
Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors Jim Tschanz, S. Narendra, R. Nair, IEEE Journal of Solid-State Circuits Low-power ElectronicsLow PowerElectrical EngineeringPhysical Design (Electronics)Engineering	2003	131
Variation-tolerant circuits Jim Tschanz, Keith Bowman, Vivek De Low-power ElectronicsElectrical EngineeringPhysical Design (Electronics)EngineeringVlsi Design	2005	64
PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction Arijit Raychowdhury, Bibiche Geuskens, Jaydeep P. Kulkarni, Pvt-and-aging Adaptive WordlineRd Evaluation PathEngineeringMemory DesignEnergy Efficiency	2010	61
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor Saurabh Dighe, Paolo Aseron, Sunil Kumar, Optimal Core MappingManycore ProcessorEngineeringVlsi DesignEnergy Efficiency	2010	58
Parameter variations and impact on circuits and microarchitecture Shekhar Borkar, Tanay Karnik, S. Narendra, Proceedings of the 40th conference on Design automation - DAC '03 Hardware SecurityLow-power ElectronicsElectrical EngineeringPhysical Design (Electronics)Engineering	2003	50
Dynamic-sleep transistor and body bias for active leakage power control of microprocessors Jim Tschanz, S. Narendra, Yibin Ye, Hardware SecurityLow-power ElectronicsPower-aware ComputingElectrical EngineeringEngineering	2003	48
Formal derivation of optimal active shielding for low-power on-chip buses Maged Ghoneima, Yehea Ismail, Muhammad Khellah, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Hardware SecurityElectrical EngineeringEngineeringOptimal Active ShieldingPower Optimization (Eda)	2006	42
20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS Harish K. Krishnamurthy, Vaibhav Vaidya, Sheldon Weng, Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignPower Device	2017	41
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors T. Karnik, Yibin Ye, Jim Tschanz, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324) EngineeringAccelerated DesignEnergy EfficiencyElectronic Design AutomationPower Optimization (Eda)	2002	37

Page 1