Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor

Abstract

Measured within-die core-to-core F¿¿¿ variation data for an 80-core processor in 65 nm is presented. Variation-aware DVFS with optimal core mapping is shown to improve energy efficiency 6 to 35% across a range of compute/communication activity workloads. A dynamic-thread-hopping scheme boosts performance by 5 to 10% and energy efficiency by 20 to 60%.