Hung‐Der Su

The influence of the layout on the ESD performance of HV-LDMOS

Jian‐Hsing Lee, Hung‐Der Su, Chien-Ling Chan et al. · International Symposium on Power Semiconductor Devices and IC's · 2010 · 28 citations

Electrical Engineering, Physical Design (Electronics), Engineering +9

0.18um BCD technology with best-in-class LDMOS from 6 V to 45 V

Tsung-Yi Huang, Wen-Yi Liao, Ching-Yao Yang et al. · 2014 · 27 citations

Electrical Engineering, Engineering, Rf Semiconductor +13

The ESD failure mechanism of ultra-HV 700V LDMOS

Jian‐Hsing Lee, Tzu‐Cheng Kao, Chien-Liang Chan et al. · 2011 · 19 citations

Esd Failure Mechanism, Electrical Engineering, Engineering +9

Simple scheme to increase hold voltage for silicon‐controlled rectifier

Chung‐Yu Hung, Tzu‐Cheng Kao, Jian‐Hsing Lee et al. · Electronics Letters · 2014 · 11 citations

Demonstration of a HV BCD technology with LV CMOS process

Tsung-Yi Huang, Chien‐Hao Huang, Chih‐Fang Huang et al. · 2015 · 10 citations