The ESD failure mechanism of ultra-HV 700V LDMOS

Abstract

A new kind of ESD failure mechanism is found in the UHV 700V LDNMOS during the HBM ESD zapping event. The device is damaged by its own charges and board stored charges, not damaged by the HBM stress current. The device junction capacitor and test-board capacitor store the charges from the ESD tester before the avalanche breakdown occurring. After the avalanche breakdown, the two capacitors discharge the stored charges to give the additional currents to stress the device. This phenomenon is called the charged-capacitor model (CCM).