2014 · 28 citations · 4 references
EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyIii-v SemiconductorsIntegrated Circuit DesignOxide SemiconductorsSemiconductor ReliabilityComplementary Metal-oxide-semiconductor DesignComplementary Metal-oxide-semiconductor DevicesEtching MasksHigh PerformanceLow-voltage Cmos Design
We propose a novel nLDMOS structure and a design concept in BCD technology with the best-in-class performance. The drift profile is optimized and the multi-oxide in the drift region is adopted to approach the RESURF limit of on-resistance vs. BVdss characteristic (i.e., 36V DMOS has a Ron_sp of 20mohm-mm2 with a BVdss of 50V; 45V DMOS has a Ron_sp of 28mohm-mm2 with a BVdss of 65V). Moreover, this modification requires merely three extra masks in the Non-Epitaxy LV process to achieve this improvement. Therefore it is not only a high performance but also a low cost solution.
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Koji Shirai, Koji Yonemura, K. Watanabe et al. · IEEE International Symposium on Power Semiconductor Devices and ICs/Proceedings of the International Symposium on Power Semiconductor Devices & ICs/Proceedings of the ... International Symposium on Power Semiconductor Devices & ICs/Proceedings of the ... International Symposium on Power Semiconductor Devices and ICs · 2009 · 45 citations
Advanced 0.13um smart power technology from 7V to 70V
Hoon Chang, Jaejune Jang, Min Hwan Kim et al. · 2012 · 26 citations