Publication | Closed Access
The influence of the layout on the ESD performance of HV-LDMOS
28
Citations
4
References
2010
Year
Electrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignHigh Voltage EngineeringElectrostatic DischargeEsd PerformanceComputer EngineeringHigh VoltageBulk LayoutLow Voltage Electrostatic-dischargeMicroelectronics
The root causes of the high voltage (HV) LDMOS (Fig. 2) failed at the low voltage electrostatic-discharge (ESD) zap is found. One is caused by the bulk layout and one is caused by the intrinsic characteristic of the device. From the findings, a new structure is proposed to eliminate the root causes without sacrificing the IV characteristics and dimension of the device.
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