D.S. Zicherman

A new 'shift and ratio' method for MOSFET channel-length extraction

Yuan Taur, D.S. Zicherman, D.R. Lombardi et al. · IEEE Electron Device Letters · 1992 · 222 citations

Device Modeling, Low-power Electronics, Electrical Engineering +9

Design and experimental technology for 0.1-µm gate-length low-temperature operation FET's

G.A. Sai-Halasz, M.R. Wordeman, D. P. Kern et al. · IEEE Electron Device Letters · 1987 · 135 citations

Low-power Electronics, Device Modeling, Electrical Engineering +15

Experimental technology and characterization of self-aligned 0.1µm-gate-length low-temperature operation NMOS devices

G.A. Sai-Halasz, M.R. Wordeman, D. P. Kern et al. · 1987 · 24 citations

Semiconductor Technology, Electrical Engineering, Engineering +12

A highly latchup-immune 1-µm CMOS technology fabricated with 1-MeV ion implantation and self-aligned TiSi₂

Fang-Shi J. Lai, L.K. Wang, Yuan Taur et al. · IEEE Transactions on Electron Devices · 1986 · 22 citations

Design and characterization of a CMOS off-chip driver/receiver with reduced power-supply disturbance

H.I. Hanafi, R.H. Dennard, C.-L. Chen et al. · IEEE Journal of Solid-State Circuits · 1992 · 17 citations

Low-power Electronics, Reduced Power-supply Disturbance, Driver-receiver Delay +14