W. Wille

Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low-k BEOL

D. Edelstein, H. Rathore, C. Davis et al. · 2004 · 23 citations

Engineering, Chip-package Reliability Stress, Interconnect (Integrated Circuits) +20

Trade-offs in the integration of high performance devices with trench capacitor DRAM

S. Crowder, S. R. Stiffler, P. Parries et al. · 2002 · 22 citations

Hardware Security, Trench Capacitor Dram, Electrical Engineering +13

High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology

Z. Luo, N. Rovedo, B. Phoong et al. · 2007 · 20 citations

Low-power Electronics, Competitive Sram, Electrical Engineering +15

Shallow Trench Isolation for the 45-nm CMOS Node and Geometry Dependence of STI Stress on CMOS Device Performance

A. Tilke, Chris Stapelmann, M. Eller et al. · IEEE Transactions on Semiconductor Manufacturing · 2007 · 19 citations

Engineering, Vlsi Design, Integrated Circuits +18

STI Gap-Fill Technology with High Aspect Ratio Process for 45nm CMOS and beyond

A. Tilke, M. Culmsee, R. Jaiswal et al. · 2006 · 18 citations

Electrical Engineering, Physical Design (Electronics), Engineering +15