2006 · 18 citations · 1 references
Electrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignFill ProcessThree-dimensional Heterogeneous IntegrationAdvanced Packaging (Semiconductors)Surface ScienceApplied PhysicsComputer EngineeringSti Gap FillSemiconductor Device FabricationElectronic PackagingSti Gap-fill TechnologyMicroelectronicsBeyond CmosChemical Vapor DepositionSti Liners
In the present work the high aspect ratio process (HARP) using a new O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /TEOS based sub atmospheric chemical vapor deposition process was implemented as STI gap fill in sub-65nm CMOS. We prove good gap fill performance up to aspect ratios larger 10:1. Since this fill process doesn't attack the STI liners as compared to HDP, a variety of different STI liners can be implemented
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