Christopher Waskiewicz

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

Kwangyou Seo, Bala Haran, Divya Gupta et al. · 2014 · 97 citations

Engineering, Vlsi Design, Finfet Technology +18

Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices

H. Jagannathan, Brett D. Anderson, C-W. Sohn et al. · 2021 IEEE International Electron Devices Meeting (IEDM) · 2021 · 59 citations

Device Modeling, Electrical Engineering, Engineering +14

BEOL Cu CMP Process Evaluation for Advanced Technology Nodes

Kunaljeet S. Tanwar, D. Canaperi, Michael Lofaro et al. · Journal of The Electrochemical Society · 2013 · 51 citations

Engineering, Mechanical Engineering, Advanced Technology Nodes +17

EUV lithography at the 22nm technology node

Obert R. Wood, Chiew-Seng Koay, Karen Petrillo et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2010 · 22 citations

Technology Node, Electrical Engineering, Wafer Scale Processing +15

56 nm pitch Cu dual-damascene interconnects with self-aligned via using negative-tone development Lithography-Etch-Lithography-Etch patterning scheme

Yannick Loquet, Yann Mignot, Christopher Waskiewicz et al. · Microelectronic Engineering · 2012 · 13 citations

Materials Science, Wafer Scale Processing, Engineering +7