J. Jopling

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

C. Auth, C. Allen, A. Blattner et al. · 2012 · 749 citations

Low-power Cmos Technology, Engineering, Vlsi Design +19

High performance 32nm logic technology featuring 2<sup>nd</sup> generation high-k + metal gate transistors

P. Packan, Sheikh A. Akbar, M Armstrong et al. · 2009 · 184 citations

Nm Logic Technology, Electrical Engineering, Engineering +13

Erratic fluctuations of sram cache vmin at the 90nm process technology node

M. Agostinelli, J. Hicks, Jianzhong Xu et al. · 2006 · 116 citations

Hardware Security, Non-volatile Memory, Electrical Engineering +15

Universal tunneling behavior in technologically relevant P/N junction diodes

P. M. Solomon, J. Jopling, D.J. Frank et al. · Journal of Applied Physics · 2004 · 106 citations

Device Modeling, Semiconductors, Electrical Engineering +13

Dielectric breakdown in a 45 nm high-k/metal gate process technology

C. Prasad, M. Agostinelli, C. Auth et al. · 2008 · 26 citations

Materials Engineering, Electrical Engineering, Semiconductor Device +15