Dan Perry

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

Geert Van der Plas, Paresh Limaye, Igor Loi et al. · IEEE Journal of Solid-State Circuits · 2010 · 308 citations

Engineering, Vlsi Design, 3-D Chip Stacks +17

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

A. Mercha, Geert Van der Plas, Victor Moroz et al. · 2010 · 119 citations

Engineering, Stress Aware Design, Mechanical Engineering +22

Design issues and considerations for low-cost 3D TSV IC technology

Geert Van der Plas, Paresh Limaye, A. Mercha et al. · 2010 · 61 citations

Engineering, Vlsi Design, Computer Architecture +16

Test structures for characterization of through silicon vias

Michele Stucchi, Dan Perry, Guruprasad Katti et al. · 2010 · 28 citations

Engineering, Computer Architecture, Silicon On Insulator +22

Test Structures for Characterization of Through-Silicon Vias

Michele Stucchi, Dan Perry, Guruprasad Katti et al. · IEEE Transactions on Semiconductor Manufacturing · 2012 · 25 citations

3D Ic Architecture, Electrical Engineering, 3-D Chip +15