N. Ramani

A 100 nm copper/low-k bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications

G.C.-F. Yeap, J. Chen, Piotr Grudowski et al. · 2003 · 21 citations

Engineering, Computer Engineering, Electrical Engineering +17

A versatile 0.13 μm CMOS platform technology supporting high performance and low power applications

A.H. Perera, B. Smith, N. Cave et al. · 2002 · 18 citations

Engineering, Computer Engineering, Electrical Engineering +17

Metrology Challenges for 45-nm Strained-Si Device Technology

Victor Vartanian, Stefan Zollner, Aaron Thean et al. · IEEE Transactions on Semiconductor Manufacturing · 2006 · 17 citations

Engineering, Electrical Engineering, Materials Science +17

A high density 0.10 μm CMOS technology using low K dielectric and copper interconnect

Shivendra Singh Parihar, M. Angyal, B. Boeck et al. · 2002 · 15 citations

Engineering, Computer Engineering, Electrical Engineering +17