A. Azuma

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

S. Inaba, K. Okano, Shôichi Matsuda et al. · IEEE Transactions on Electron Devices · 2002 · 75 citations

Low-power Electronics, Nitrogen Concentration, Electrical Engineering +12

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

E. Leobandung, H. Nayakama, D. Mocuta et al. · 2005 · 65 citations

Electrical Engineering, Engineering, Vlsi Design +15

Performance improvement of metal gate CMOS technologies

Shôichi Matsuda, Hiroshi Yamakawa, A. Azuma et al. · 2002 · 19 citations

Low-power Electronics, High Speed Applications, Electrical Engineering +12

In situ Doped Embedded-SiGe Source/Drain Technique for 32 nm Node p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor

H. Okamoto, A. Hokazono, K. Adachi et al. · Japanese Journal of Applied Physics · 2008 · 16 citations

A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32nm node and beyond

Nobuaki Yasutake, A. Azuma, Tatsuya Ishida et al. · Solid-State Electronics · 2007 · 13 citations

Electrical Engineering, Sige-s/d Structure, Engineering +8