S. Ratanaphanyarat

A 0.25 μm CMOS SOI technology and its application to 4 Mb SRAM

D. Schepis, F. Assaderaghi, D. S. Yee et al. · 2002 · 51 citations

Engineering, Computer Engineering, Electrical Engineering +12

SRAM bitline circuits on PD SOI: advantages and concerns

J.B. Kuang, S. Ratanaphanyarat, M.J. Saccamango et al. · IEEE Journal of Solid-State Circuits · 1997 · 22 citations

Engineering, Computer Engineering, Electrical Engineering +15

Schottky-collector vertical PNM bipolar transistor

Shahnaz Akbar, S. Ratanaphanyarat, J.B. Kuang et al. · Electronics Letters · 1992 · 12 citations

Engineering, Electrical Engineering, Microelectronics +15

Effect of emitter contact materials on high-performance vertical p-n-p transistors

S. Ratanaphanyarat, W. Rausch, Mithkal M. Smadi et al. · IEEE Electron Device Letters · 1991 · 10 citations

Engineering, Electrical Engineering, Materials Science +17