Douglas W. Barlage

30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays

R. Chau, J. Kavalieros, B. Roberds et al. · 2002 · 110 citations

Electrical Engineering, Engineering, Vlsi Design +11

A 50 nm depleted-substrate CMOS transistor (DST)

R. Chau, J. Kavalieros, Barry M. Doyle et al. · 2002 · 101 citations

Electrical Engineering, Engineering, Nanoelectronics +11

Zinc oxide thin film transistors with Schottky source barriers

Michael Alex, Manisha Gupta, Fatema Rezwana Chowdhury et al. · Solid-State Electronics · 2012 · 64 citations

Electrical Engineering, Engineering, Oxide Electronics +3

Inversion MOS capacitance extraction for high-leakage dielectrics using a transmission line equivalent circuit

Douglas W. Barlage, J.T. O'Keeffe, J. Kavalieros et al. · IEEE Electron Device Letters · 2000 · 52 citations

Device Modeling, Electrical Engineering, Semiconductor Device +12

High-frequency response of 100 nm integrated CMOS transistors with high-K gate dielectrics

Douglas W. Barlage, Reza Arghavani, G. Dewey et al. · 2002 · 46 citations

Pmos Transistors, Electrical Engineering, Engineering +13