J. Li

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

N. Loubet, Terence B. Hook, P. Montanini et al. · 2017 · 939 citations

Engineering, Nanocomputing, Semiconductor Device +17

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

Ruijie Xie, P. Montanini, Kerem Akarvardar et al. · 2016 · 139 citations

Engineering, Electron-beam Lithography, Finfet Technology +18

A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

X. Chen, S. Samavedam, Vijay Narayanan et al. · 2008 · 112 citations

Low-power Electronics, Low Power Applications, Electrical Engineering +14

Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications

J. Zhang, Julien Frougier, Andrew Greene et al. · 2019 · 93 citations

Engineering, Semiconductor Device, Advanced Packaging (Semiconductors) +17

High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET

K. Cheng, A. Khakifirooz, N. Loubet et al. · 2012 · 74 citations