Kwan Weon Kim

25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV

Dong Uk Lee, Kyung Whan Kim, Kwan Weon Kim et al. · 2014 · 247 citations

Engineering, Computer Engineering, Computer Science +11

A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits

Dong Uk Lee, Kyung Whan Kim, Kwan Weon Kim et al. · IEEE Journal of Solid-State Circuits · 2014 · 105 citations

Engineering, Computer Engineering, Electrical Engineering +14

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

Won-Joo Yun, Hyun‐Woo Lee, Dongsuk Shin et al. · 2008 · 33 citations

Engineering, Computer Engineering, Electrical Engineering +16

A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL

Dong Uk Lee, Hyun‐Woo Lee, Ki Chang Kwean et al. · 2006 · 28 citations

Engineering, Computer Engineering, Electrical Engineering +17

An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM

Dong Uk Lee, Kyung Whan Kim, Kwan Weon Kim et al. · 2014 · 18 citations

Engineering, Computer Engineering, Electrical Engineering +12