IEEE Journal of Solid-State Circuits · 2014 · 105 citations · 19 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMemoryMicroelectronicsMemory DevicesMemory HierarchyMemory Subsystem DesignBandwidthGraphics Memory SystemsHigh Bandwidth MemoryMemory Array ArchitectureMemory BandwidthMemory Circuit DesignMemory Interface DesignMemory Test
HBM DRAM introduces a new architecture that multiplies bandwidth across multiple memories, addressing numerous technical challenges. The chip employs a stacked memory with TSV arrays, semi‑independent command interfaces, and fine‑pitch microbump contacts, fabricated via a chip‑on‑wafer process and validated with high‑frequency wafer probing. Chip‑on‑wafer testing demonstrates 128 GB/s bandwidth at 1.2 V.
Motivated by a graphics memory system that achieves multiplied bandwidth by the number of memories per system, HBM DRAM adopts a brand new architecture, with many technical changes and challenges. The first main change in the architecture is the stacked memory structure with TSV array, which has independent bandwidth per slice. The second is semi-independent row, column command interface, which enhances effective performance. For supporting high bandwidth, this chip has fine pitch microbump interface. Methods for testing microbump are explained. 8 Gb stacked HBM is fabricated with chip-on-wafer process and tested with high-frequency wafer probing. Using chip-on-wafer test results, 128 GB/s at 1.2 V supply voltage is achieved.
19
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology
Uksong Kang, Hoeju Chung, Seongmoo Heo et al. · IEEE Journal of Solid-State Circuits · 2010 · 487 citations
Engineering, Computer Engineering, Electrical Engineering +15