2006 · 28 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSystem-on-chip DesignDynamic Power ReductionEmbedded Memory BlocksLow-power Digital Circuit DesignMemory Hierarchy DesignMemory Subsystem DesignTiming AnalysisGddr Memory SystemsLatch DesignLow-latency DesignLow-power Memory ArchitectureLow-power Memory CircuitsNoise ImmunityPower ConsumptionVoltage-dependent Delay
A series pipelined CAS latency control with voltage-controlled delay line that extends maximum data rate to 2.5Gb/s/pin at 1.7V, is presented. Other schemes applied in the DLL are dual loop control that increases power noise immunity and LPDCC that achieves low power consumption. All these schemes are implemented in a 8M times 32 device using a 0.10 mum DRAM process
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