Young Jung Choi

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

Won-Joo Yun, Hyun‐Woo Lee, Dongsuk Shin et al. · 2008 · 33 citations

Engineering, Computer Engineering, Electrical Engineering +16

A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL

Dong Uk Lee, Hyun‐Woo Lee, Ki Chang Kwean et al. · 2006 · 28 citations

Engineering, Computer Engineering, Electrical Engineering +17

Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface

Dong Uk Lee, Shin Deok Kang, Nak Kyu Park et al. · 2008 · 13 citations

Engineering, Computer Engineering, Electrical Engineering +9

A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC

Dongsuk Shin, Janghoon Song, Hyunsoo Chae et al. · 2007 · 10 citations

Engineering, Electrical Engineering, Analog Electronics +15