Y. Niitsu

0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file

Hiroyuki Hara, T. Sakurai, T. Nagamatsu et al. · IEEE Journal of Solid-State Circuits · 1992 · 20 citations

Engineering, Computer Engineering, Electrical Engineering +17

Impurity diffusion behavior of bipolar transistor under low-temperature furnace annealing and high-temperature RTA and its optimization for 0.5- mu m Bi-CMOS process

M. Norishima, Hiroshi Iwai, Y. Niitsu et al. · IEEE Transactions on Electron Devices · 1992 · 18 citations

Engineering, Electrical Engineering, Materials Science +17

0.8µm Bi-CMOS technology with high f<inf>T</inf>ion-implanted emitter bipolar transistor

Hiroshi Iwai, Gen Sasaki, Y. Unno et al. · 1987 · 17 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 400Mb/s 8x8 BICMOS ATM Switch LSI With 1280 On-chip Shared Memory

S. Tanaka, Yasuro Shobatake, K. Sakaue et al. · 1991 · 13 citations

Computing, Communication, Computer Engineering +15

0.5- mu m 2 M-transistor BiPNMOS channelless gate array

Hiroyuki Hara, T. Sakurai, Makoto Noda et al. · IEEE Journal of Solid-State Circuits · 1991 · 11 citations

Engineering, Computer Engineering, Electrical Engineering +15