Kazuhiko Matsuo

Improvement of threshold voltage deviation in damascene metal gate transistors

A. Yagishita, Tomohiro Saito, K. Nakajima et al. · IEEE Transactions on Electron Devices · 2001 · 76 citations

Engineering, Electrical Engineering, Materials Science +17

High-Performance FinFET with Dopant-Segregated Schottky Source/Drain

A. Kaneko, A. Yagishita, K. Yahashi et al. · 2006 · 53 citations

Engineering, Electrical Engineering, Electronic Materials +11

Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension

A. Kaneko, A. Yagishita, K. Yahashi et al. · 2006 · 44 citations

Engineering, Electrical Engineering, Low-power Design +11

Performance Maximization of In-Memory Reinforcement Learning with Variability-Controlled Hf_1-xZr_xO₂ Ferroelectric Tunnel Junctions

K. Ota, M. Yamaguchi, Radu Berdan et al. · 2019 · 24 citations

Engineering, Computer Engineering, Electrical Engineering +9

A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL

H. Nii, T. Sanuki, Y. Okayama et al. · 2006 · 22 citations

Engineering, Computer Engineering, Electrical Engineering +14