Nikolaos Minas

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

Geert Van der Plas, Paresh Limaye, Igor Loi et al. · IEEE Journal of Solid-State Circuits · 2010 · 308 citations

Engineering, Computer Engineering, Electrical Engineering +17

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

A. Mercha, Geert Van der Plas, Victor Moroz et al. · 2010 · 119 citations

Engineering, Computer Engineering, Electrical Engineering +17

A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability

Nikolaos Minas, D.J. Kinniment, Keith Heron et al. · Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems · 2007 · 20 citations

Engineering, Computer Engineering, Electrical Engineering +12

Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance

A. Mercha, A. Redolfi, Michele Stucchi et al. · 2010 · 16 citations

Engineering, Electrical Engineering, Materials Science +17

Test structures for characterization of thermal-mechanical stress in 3D stacked IC for analog design

Nikolaos Minas, Geert Van der Plas, Herman Oprins et al. · 2010 · 15 citations

Engineering, Electrical Engineering, Microelectronics +16