S. Lee - Concepedia

Author

S. Lee

Intel (United States)

Also Known As

S. Lee, Sai Link Lee, Sudarat Lee

Publications

392

Citations

H-Index

Concepts

All Affiliations

Intel (United States)

About

S. Lee is an author at Intel (United States) specializing in engineering, microelectronics, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	5	5	324
2	Applied Physics	3	3	187
3	Chemical Engineering	1	1	108
4	Chemistry	1	1	31
5	Computer Engineering	1	1	29

S. Lee

Publications

384

Citations

H-Index

Page 1

	Year	Citations
Advancing 2D Monolayer CMOS Through Contact, Channel and Interface Engineering Kevin P. O’Brien, C. J. Dorow, Ashish Verma Penumatcha, 2021 IEEE International Electron Devices Meeting (IEDM) EngineeringTransition Metal DichalcogenideOptoelectronic DevicesSemiconductorsIi-vi Semiconductor	2021	109
Effect of Pressure, Subcooling, and Dissolved Gas on Pool Boiling Heat Transfer From Microporous Surfaces in FC-72 Kevin Rainey, S. M. You, S. Lee Journal of Heat Transfer EngineeringBoiling PerformanceNucleate BoilingConvective Heat TransferDissolved Gas	2003	108
Gate length scaling beyond Si: Mono-layer 2D Channel FETs Robust to Short Channel Effects C. J. Dorow, Ashish Verma Penumatcha, A. Kitamura, 2022 International Electron Devices Meeting (IEDM) EngineeringTwo-dimensional MaterialsChannel FetSemiconductor DeviceChannel Fets Robust	2022	47
300 mm MOCVD 2D CMOS Materials for More (Than) Moore Scaling K. Maxey, Carl H. Naylor, Kevin P. O’Brien, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) EngineeringMore MooreTwo-dimensional MaterialsChemistryChemical Deposition	2022	31
Enabling high-performance mixed-signal system-on-a-chip (SoC) in high performance logic CMOS technology L.M. Franca-Neto, Patrick Pardy, Montliy Ly, EngineeringVlsi DesignAnalog DesignComputer ArchitectureHigh-performance Mixed-signal System-on-a-chip	2003	29
High Mobility TMD NMOS and PMOS Transistors and GAA Architecture for Ultimate CMOS Scaling Ashish Verma Penumatcha, Kevin O’Brien, K. Maxey,	2023	21
Record Performance in GAA 2D NMOS and PMOS Using Monolayer MoS2 and WSe2 with Scaled Contact and Gate Length Wouter Mortelmans, Pratyush Buragohain, Carly Rogan,	2024	18
Reliability Assessment of Double-Gated Wafer-Scale MoS<sub>2</sub> Field Effect Transistors through Hysteresis and Bias Temperature Instability Analyses Alexandros Provias, Theresia Knobloch, A. Kitamura,	2023	11
Gate Oxide Module Development for Scaled GAA 2D FETs Enabling SS<75mV/d and Record Idmax>900μA/μm at Lg<50nm Wouter Mortelmans, Pratyush Buragohain, A. Kitamura,	2024	10

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