Gate length scaling beyond Si: Mono-layer 2D Channel FETs Robust to Short Channel Effects

Abstract

We explore 2D channel FET scaling down to Source-to-Drain contact spacing (L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S-D</inf> ) of 25 nm, comparable to state-of-the-art Si technology. Single gated devices show an uptick in subthreshold slope (SS) when scaling below $\mathrm{L}_{S-D}\,=34\mathrm{nm}$. Double gate devices, fabricated by use of a thin high-k bilayer ALD process optimized for 2D material surfaces, enhance electrostatics to achieve steep SS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</inf> of 75 mV/dec and low DIBL of 12 mV/V for long L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S-D</inf> devices. Nearly zero hysteresis and preliminary BTI studies show gate oxide health is promising, but improvements are needed to match Si. TCAD simulations fitted to the experimental data confirm 2D channel transistors as suitable candidates for the replacement of Si to enable a long future of Moore's Law scaling.