D.-G. Park

High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm 2 SRAM and ultra low-k back end with eleven levels of copper

B. Greene, Qingqing Liang, K. Amarnath et al. · Symposium on VLSI Technology · 2006 · 40 citations

Engineering, Computer Engineering, Electrical Engineering +15

Understanding short-term BTI behavior through comprehensive observation of gate-voltage dependence of RTN in highly scaled high-κ / metal-gate pFETs

H. Miki, Masami Yamaoka, Naoki Tega et al. · 2011 · 26 citations

Engineering, Electrical Engineering, Microelectronics +16

Reduction of random telegraph noise in High-к / metal-gate stacks for 22 nm generation FETs

Naoki Tega, Hiroshi Miki, Zhibin Ren et al. · 2009 · 25 citations

Engineering, Electrical Engineering, Materials Science +17

Thermally robust dual-work function ALD-MN/sub x/ MOSFETs using conventional CMOS process flow

D.-G. Park, Z. Luo, N.L. Edleman et al. · 2004 · 24 citations

Engineering, Electrical Engineering, Materials Science +17