Systematical study of 14nm FinFET reliability: From device level stress to product HTOL

Changze Liu, Hyun Chul Sagong, Hyejin Kim, +10

ReliabilityElectrical EngineeringProduct HtolEngineeringVlsi Design +12

Considering physical mechanisms and geometry dependencies in 14nm FinFET circuit aging and product validations

Sangwoo Pae, Hyun Chul Sagong, C. Liu, +12

Device ModelingElectrical EngineeringEngineeringProduct ValidationsExtensive 14Nm +13

Analytic Model of S/D Series Resistance in Trigate FinFETs With Polygonal Epitaxy

Chang-Woo Sohn, Chang Yong Kang, Myung-Dong Ko, +10

IEEE Transactions on Electron Devices

Device ModelingElectrical EngineeringEngineeringPhysicsNanoelectronics +9

A systematic study of gate dielectric TDDB in FinFET technology

Hyunjin Kim, Minjung Jin, Hyun Chul Sagong, +6

Device ModelingElectrical EngineeringSemiconductor DeviceEngineeringAdvanced Packaging (Semiconductors) +12

Reliability on Evolutionary FinFET CMOS Technology and Beyond

Kihyun Choi, Hyun Chul Sagong, Minjung Jin, +11

EngineeringVlsi DesignFinfet TechnologyScaled FinfetReliability Engineering +14

Device Design Guidelines for Nanoscale FinFETs in RF/Analog Applications

Chang-Woo Sohn, Chang Yong Kang, Rock‐Hyun Baek, +7

IEEE Electron Device Letters

Low-power ElectronicsDevice ModelingElectrical EngineeringDevice Design GuidelinesEngineering +10

Modeling of FinFET Self-Heating Effects in multiple FinFET Technology Generations with implication for Transistor and Product Reliability

Hyun Chul Sagong, Kiho Choi, J. Kim, +7

Finfet Self-heating EffectsEngineeringFinfet Self-heatingNanoelectronicsFsh Effects +14

Enhanced Reliability of 7-nm Process Technology Featuring EUV

Kihyun Choi, Hyewon Shim, Junekyun Park, +11

IEEE Transactions on Electron Devices

EngineeringComputer ArchitectureScaled FinfetEnhanced ReliabilityReliability Engineering +14

Investigation of alpha-induced single event transient (SET) in 10 nm FinFET logic circuit

Taiki Uemura, Soon Young Lee, Dahye Min, +5

Electrical EngineeringSingle Event UpsetEngineeringVlsi DesignPhysics +9

Analysis of Abnormal Upturns in Capacitance–Voltage Characteristics for MOS Devices With High-$k$ Dielectrics

Chang-Woo Sohn, Hyun Chul Sagong, Eui-Young Jeong, +6

IEEE Electron Device Letters

Electrical EngineeringCapacitance–voltage CharacteristicsEngineeringMos DevicesDielectric Samples +9