A systematic study of gate dielectric TDDB in FinFET technology

Abstract

A systematic study of HK/MG TDDB on FinFETs are discussed on this paper. In addition to conventional inversion based TDDB modeling, accumulation mode and AC TDDB are also important for correctly assessing product level gate oxide dppms and remove conservatism. Through extensive characterizations, we'll show that the Ninv and Pacc mode and Nacc and Pinv TDDB behaviors are physically similar and mainly polarity dependent. By employing all 4 gate oxide models (N/P, inv/acc) including on/off-state mode and with AC-TDDB modeling on product, significantly reduced dppm can be achieved that can explain the generally large gap observed between wafer-level DC based TDDB and product level HTOL that represents well beyond the DC gate models, extending the technology Vmax headroom without reliability tradeoffs.