S. Wang

First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers

S. Subramanian, M. Reza Hosseini, T. Chiarella et al. · 2020 · 119 citations

Engineering, Electrical Engineering, Microelectronics +16

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning

Hans Mertens, Maryam Hosseini, T. Chiarella et al. · 2023 · 54 citations

Engineering, Electrical Engineering, Materials Science +14

Buried Power Rail Metal exploration towards the 1 nm Node

Anshul Gupta, D. Radisic, Jan Willem Maes et al. · 2021 IEEE International Electron Devices Meeting (IEDM) · 2021 · 23 citations

Engineering, Electrical Engineering, Materials Science +17

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

A. Veloso, Anne Jourdain, D. Radisic et al. · IEEE Transactions on Electron Devices · 2022 · 21 citations

Engineering, Electrical Engineering, Electronic Materials +12

Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond

Anshul Gupta, Olalla Varela Pedreira, Hans Mertens et al. · 2020 · 15 citations

Engineering, Electrical Engineering, Materials Science +17