Kenny Hsieh - Concepedia

Author

Kenny Hsieh

Taiwan Semiconductor Manufacturing Company (Taiwan)

Also Known As

K. Hsieh, Kenny C. H. Hsieh, Kenny Cheng-Hsiang Hsieh, Kenny Hsieh, Kunta Hsieh

Publications

350

Citations

H-Index

Concepts

All Affiliations

Taiwan Semiconductor Manufacturing Company (Taiwan)Xilinx (United States)University College Dublin University of California, Berkeley Taiwan Semiconductor Manufacturing Company (United States)

About

Kenny Hsieh is an author at Taiwan Semiconductor Manufacturing Company (Taiwan) specializing in computer engineering, engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	8	8	254
2	Computer Engineering	8	8	225
3	Electrical Engineering	6	6	199
4	Computer Architecture	5	5	182
5	Advanced Packaging	1	1	85

Kenny Hsieh

Publications

290

Citations

H-Index

Page 1

	Year	Citations
A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing Mu-Shan Lin, Tze-Chiang Huang, Chien-Chun Tsai, IEEE Journal of Solid-State Circuits Octo-core ProcessorInter-chiplet LinkVlsi DesignEngineeringComputer Architecture	2020	85
19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications Chao-Chieh Li, Min-Shueh Yuan, Chih-Hsien Chang, EngineeringEnergy EfficiencyDc-dc ConverterPower ElectronicsEh Output Voltage	2017	41
A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS Jafar Savoj, Kenny Hsieh, Parag Upadhyaya, 5-Tap Speculative DfeEngineeringVlsi DesignClock RecoveryMixed-signal Integrated Circuit	2012	29
A 0.5–16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS Yohan Frans, Declan Carey, Marc Erett, IEEE Journal of Solid-State Circuits Transceiver MeetsEngineeringVlsi DesignClock RecoveryMixed-signal Integrated Circuit	2015	26
Design of high-speed wireline transceivers for backplane communications in 28nm CMOS Jafar Savoj, Kenny Hsieh, Parag Upadhyaya, Electrical EngineeringBackplane CommunicationsEngineeringVlsi DesignVlsi Architecture	2012	24
2nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects Co-Optimized with 3DIC for AI, HPC and Mobile SoC Applications Geoffrey Yeap, Shiwei Lin, Huiling Shang,	2024	24
A Low-Power 0.5–6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs Jafar Savoj, Kenny Hsieh, Fu-Tai An, IEEE Journal of Solid-State Circuits Low-power ElectronicsPower ConsumptionElectrical EngineeringLow-cost 28Engineering	2013	18
A Hybrid-PLL (ADPLL/Charge-Pump PLL) Using Phase Realignment With 0.6-us Settling, 0.619-ps Integrated Jitter, and −240.5-dB FoM in 7-nm FinFET Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, IEEE Solid-State Circuits Letters Electrical Engineering7-Nm FinfetEngineeringAdpll/charge-pump PllClock Recovery	2020	17
A 700 Mb/s BiCMOS read channel integrated circuit S.A. Altekar, Hin-Tat Chan, Jenn-Gang Chern, Rate EprmlElectrical EngineeringRead Channel IcDb Snr ImprovementVlsi Design	2002	14
A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET Dirk Pfaff, Shahaboddin Moazzeni, Leisheng Gao, Sst TransmitterFinfet TechnologyMixed-signal Integrated CircuitComputer EngineeringPam-4 Transceiver	2019	12

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