A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS

Abstract

This paper describes the design of a fully-adaptive backplane transceiver embedded in a state-of-the-art, low-leakage, 28nm CMOS FPGA. The receive AFE utilizes a three-stage CTLE to provide selective frequency boost for long-tail ISI cancellation. A 5-tap speculative DFE removes the immediate post-cursor ISI. Both CTLE and DFE are fully adaptive using sign-sign LMS algorithm. A novel clocking technique uses wideband LC and ring oscillators for reliable clocking from 0.6-12.5Gb/s operation. The transmitter utilizes a 3-tap FIR and provides flexibility for supply and ground referenced operation. The transceiver achieves BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-15</sup> over a 33dB-loss backplane at 12.5Gb/s and over channels with 10G-KR characteristics at 10.3125Gb/s.