PLANARIZATION AND INTEGRATION OF SHALLOW TRENCH ISOLATION

Abstract

STI process flow and planarization requirements are reviewed. An STI planarization mask was designed and utilized for test wafer patterning to investigate STI CMP planarization. Test wafers were processed through a typical STI process sequence, including trench etch, trench liner oxidation, trench-fill, and CMP. Two different CVD techniques, ozone TEOS thermal CVD and HDPCVD, were investigated for trench-fill. CMP experiments were carried out with different process parameters and consumables. Extensive CMP characterization was carried out utilizing multiple metrology techniques. The results fit the previously reported “CMP dielectric planarization” model [1, 2] quite well.