Package-Level Interconnect Design for Optimum Electrical Performance

Abstract

This paper presents an overview of the electrical analysis and electrical design processes and techniques used to develop package-level interconnect technologies to meet Intel’s present and future performance challenges. The three areas of focus in electrical design of package interconnects: signal integrity, power delivery, and electromagnetic compatibility are discussed. Details of technology development and design choices made to meet the electrical performance requirements of some of Intel’s most recent products are discussed. Some of the specific topics discussed include design and analysis flows, design techniques for impedance control and improved signal integrity, power decoupling solutions, voltage regulation module (VRM) analysis, and design for EMI control and improvement. Design and technology trade offs to meet the varied cost goals for different product lines resulting from Intel’s recent market segmentation are also discussed using examples such as Intel’s high-end server product line, Itanium processors, and Intel’s value-PC line, Celeron processors. The importance of die-to-motherboard design integration early in the technology development cycle is also highlighted as critical in optimizing design for performance and cost.