Investigation of candidate VRM topologies for future microprocessors

TLDR

Current high‑speed CMOS processors operate above 300 MHz at 2.5–3.3 V, while future chips will target 1.1–1.8 V, creating highly dynamic loads that demand VRMs with high power density, efficiency, and transient performance. The paper addresses the critical technical issues required to achieve faster, lower‑power, highly integrated data processing systems by reducing supply voltage. The authors propose an interleaved quasisquare‑wave (QSW) VRM topology. Design, simulation, and experimental results of the proposed QSW VRM are presented.

Abstract

By reducing the power supply voltage, faster, lower power consumption, and high integration density data processing systems can be achieved. The current generation high-speed complementary metal-oxide-semiconductor (CMOS) processors (e.g., Alpha, Pentium, Power PC) are operating at above 300 MHz with 2.5 to 3.3 V output range. Future processors will be designed in the 1.1-1.8 V range, to further enhance their speed-power performance. These new generation microprocessors will present very dynamic loads with high current slew rates during transient. As a result, they will require a special power supply, voltage regulator module (VRM), to provide well-regulated voltage. The VRMs should have high power densities, high efficiencies, and good transient performance. In this paper, the critical technical issues to achieve this target for future generation microprocessors are addressed. A VRM candidate topology, interleaved quasisquare-wave (QSW), is proposed. The design, simulation and experimental results are presented.